FIG. 5 is a perspective view showing a prior art infrared imaging device. In FIG. 5, reference numeral 1 designates a two-dimensional photodiode array, for example, 128.times.128 array of pixels, which converts lights to electricity to generate signal charges. The photodiode array 1 is mounted on and electrically connected to a silicon CCD 2 for transferring signal charges, via indium bumps 3. Infrared light 4 is incident on the photodiode array 1.
FIG. 6 is a cross-sectional view of the infrared imaging device shown in FIG. 5. In FIG. 6, the same reference numerals as in FIG. 5 designate the same or corresponding parts. A p type HgCdTe layer 12 is disposed on a CdTe substrate 11. A plurality of n type impurity regions 13 are disposed at the surface of the p type HgCdTe layer 12. Each n type impurity region 13 is part of a pixel of the two-dimensional photodiode array 1. A p side electrode 5, which is common to all pixels of the photodiode array, is disposed on the p type HgCdTe layer 12 where the n type impurity regions 13 are not present. An insulating film 101 covers the HgCdTe layer 12 and the p side electrode 5 and apertures corresponding to the n type impurity regions 13 penetrate the insulating film 101. N side electrodes 6 for the pixels are formed in the apertures. N type regions 22 are disposed at the surface of the p type silicon substrate 21 of the silicon CCD 2 and opposed to the pixel regions 13 of the photodiode array 1. The n type regions 22 serve as a signal input stage of the CCD 2. An insulating film 102 having apertures corresponding to the n type regions 22 covers the silicon substrate 21 and electrodes 7 are disposed in the apertures. The n side electrode 6 of each pixel of the photodiode array 1 is connected to the opposite electrode 7 at the input stage of the CCD 2 via a corresponding indium bump 3. The p side electrode 5 is connected to the p type region of the CCD 2 via the indium bumps 3 and a substrate voltage (GND) of the CCD 2 is applied to the p side electrode 5 through the bonding pad 103 and the aluminum wiring 104.
FIG. 7 is a schematic diagram showing a two-dimensional photodiode array. A 3.times.3 pixel array is employed for simplifying the description. In FIG. 7, the p side electrode 5 is common to all pixels and an n side electrode 6 is provided corresponding to each pixel of the photodiode array 1.
FIG. 8 is a schematic diagram showing a structure of the CCD 2 from the input stage to the CCD channel and the potentials at respective regions. This CCD is a charge storage type CCD having a charge storage region at the input stage. The n side electrode of the photodiode 1 is connected to the n type region 22 of the CCD. An input stage region 25 includes the n type region 22, and an input gate region 26 is adjacent to the input stage region 25. A charge storage region 27 is adjacent to the input gate region 26. A transfer gate region 28 is adjacent to the charge storage region 27. A CCD channel region 29 is adjacent to the transfer gate region 28. An input gate electrode 17 is disposed on the input gate region 26. The potential barrier of the input gate region 26 depends on a DC voltage V.sub.G applied to the input gate electrode 17, whereby the quantity of charge transferred from the input stage region 25 to the storage region 27 is controlled. An electrode 18 forms the potential well, i.e., storage region 27 and a prescribed voltage V.sub. T is applied to the electrode 18. A transfer gate electrode 19 is disposed on the transfer gate region 28. The potential of the transfer gate region 28 is varied by applying a signal .phi..sub.T to the transfer gate electrode 19 with a prescribed timing, whereby the charges stored in the storage region 27 are transferred to the CCD channel region 29. A transfer electrode 20 is disposed on the CCD channel region 29 and a signal .phi..sub.CCD is applied to the transfer electrode 20 with a prescribed timing, whereby the charges in the CCD channel region 29 are transferred over CCD channels successively.
FIG. 9 is an electric circuit diagram of the photodiode array 1 shown in FIG. 5. In FIG. 9, reference numeral 9 designates a pixel disposed in the center of the photodiode array 1 and reference numeral 8 designates pixels surrounding the pixel 9. Reference numeral 10 designates substrate resistances (r, R) between those pixels. FIG. 10 shows I - V characteristics of the pixels.
A description is given of the operation. The p side electrode 5, which is common to all pixels, is provided around the pixels and electrically connected to the substrate voltage (GND) of the silicon CCD 2 while the n side electrodes 6 are electrically connected to the silicon CCD 2 via the In bumps 3. The infrared light 4 incident on the photodiode array 1 is converted into signal charges and the signal charges are transferred to the silicon CCD 2 through the indium bumps 3. Thereafter, the signal charges are output as time sequence signals, resulting in picture signals.
By applying a low DC voltage V.sub.G to the input gate electrode 17 of the silicon CCD as shown in FIG. 8, the quantity of charges transferred through the indium bumps can be controlled. Furthermore, a reverse bias voltage V.sub.bb is applied to each pixel of the photodiode array 1 according to the DC voltage V.sub.G. FIG. 9 shows an electric circuit diagram for explaining the voltage applied to the pixels of the photodiode array 1. In FIG. 9, the distance from the common p side electrode 5 to the peripheral pixel 8 is different from that to the central pixel 9, so that differences arise in the substrate resistances 10, resulting in differences in the reverse bias voltages V.sub.bb applied to the pixels. More concretely, when the reverse bias voltages applied to the peripheral pixel 8 and the central pixel 9 are V.sub.a and V.sub.b, respectively, and the photoelectric currents flowing through the peripheral pixel 8 and the central pixel 9 are i.sub.a and i.sub.b, respectively, the following equations are obtained. ##EQU1## As seen from above equations, the reverse bias voltage V.sub.b applied to the central pixel 9 is less than the reverse bias voltage V.sub.a applied to the peripheral pixel 8. When this result is applied to FIG. 10, the operating bias point of the peripheral pixel 8 is different from that of the central pixel 9, resulting in a difference in the output photoelectric current between the peripheral pixel 8 and the central pixel 9. More concretely, less photoelectric current is output from the central pixel 9 than from the peripheral pixel 8.
In the prior art infrared imaging device constituted as described above, there is a non-uniformity in the photoelectric current output from the peripheral pixels and the photoelectric current output from the central pixel. This problem may be solved by forming the p side electrode close to each pixel, but that solution is technically difficult. In addition, since the operating point of the device is its reverse-biased point, the device is easily affected by leakage current.